1. Field of the Invention
The present invention relates to a component built-in wiring substrate in which a plate-shaped component such as a ceramic capacitor is built and a manufacturing method thereof.
2. Description of the Related Art
Recently, there has been an increase in the speed and level of the function of semiconductor integrated circuit elements (IC chips) that are used as microprocessors of computers and the like. Accompanying such a trend, the number of terminals of the IC chips has been increased, and the pitch between the terminals has been decreased. Generally, on the bottom of the IC chip, a plurality of terminals are densely disposed in an array shape, and such a terminal group is connected to a terminal group of the motherboard side in the form of a flip-chip. However, there is a large difference in the pitch of the terminals between the terminal group of the IC chip side and the terminal group of the motherboard side. Thus, it is difficult to connect the IC chip directly to the motherboard. Accordingly, frequently, a technique is employed in which a package formed by mounting the IC chip on the wiring substrate for IC chip mounting is manufactured, and the package is mounted on the motherboard. In the wiring substrate for IC chip mounting that configures such type of package, a technique in which a condenser (also referred to as a “capacitor”) is disposed for reducing the switching noise of the IC chip and stabilizing the power source voltage has been proposed. As an example, a wiring substrate has been proposed in which a ceramic capacitor having approximately a plate shape is buried in a core substrate made of a high molecular weight material, and buildup layers are formed on the front face and the rear face of the core substrate (for example, see Patent Document 1).
In particular, in the wiring substrate disclosed in Patent Document 1, the ceramic capacitor is housed in a housing hole portion that is formed on the core substrate made of a resin, and a gap between the inner wall face of the housing hole portion and the ceramic capacitor is filled with a molding resin (resin filling portion) that is formed of an epoxy resin or the like. In addition, on the wiring substrate disclosed in Patent Document 1, terminal pads used for connection to the IC chip are formed in an array shape on one buildup layer, and terminal pads used for connecting to the motherboard are formed in an array shape on the other buildup layer. In addition, in the wiring substrate, solder bumps are disposed in the terminal pads that are disposed on the mounting surface for the IC chip.
[Patent Document 1] Japanese Unexamined Patent Application
Publication No. 2007-103789-A (FIG. 1, etc.)
3. Problems to be Solved by the Invention
The core substrate, the ceramic capacitor and the resin filling portion, which configure the above-described wiring substrate, have different coefficients of thermal expansion (CTE), and accordingly, there are cases where the uppermost layer of the wiring substrate swells due to a mismatch in the coefficients of thermal expansion. Even when a wiring substrate on which an IC chip is not mounted swells by being heated up to the solder melting temperature in a manufacturing process, the swelling disappears as the temperature decreases. However, when an IC chip is mounted on the wiring substrate using a soldering method, solidification of the solder begins before the swelling disappears. Accordingly, the shape of the swelling at that moment is maintained. In such a case, there may be a problem in that the solder bumps are thickened under the influence of the swelling so as to form a short circuit.
In the wiring substrate having the above-described configuration, when the size of the ceramic capacitor to be built into the wiring substrate is larger than that of the IC chip, and the IC chip mounting area is set so as to overlap the upper side of the resin filling portion (for example, the wiring substrate of Patent Document 1), the swelling of the uppermost layer of the substrate becomes small, and thereby there is a low possibility of the solder bumps forming a short circuit. On the contrary, in a wiring substrate in which the size of the IC chip is larger than that of the ceramic capacitor, and an IC chip mounting area larger than the resin filling portion is configured, the swelling of the uppermost layer becomes large, and thus there is high possibility of the solder bumps forming a short circuit.